The present invention generally relates to semiconductor device manufacturing, and more particularly to fabrication of a gate spacer using oxidation.
Sidewall spacers provide many fundamental functions in semiconductor processing. For example, typically following gate structure formation, a source/drain extension implantation process is performed in order to form source/drain extension regions with relatively low doping levels immediately adjacent to a gate structure. Next, gate sidewall spacers are formed. These gate sidewall spacers subsequently function as masks (i.e., as shields) during a source/drain region implantation process. The source/drain region implant process forms source/drain regions with relatively high doping levels offset from the gate structure by the width of the gate sidewall spacers (i.e., aligned to the gate sidewall spacers). Such sidewall spacers may similarly be used as masks (i.e., as shields) during other process steps, including but not limited to, salicide formation and/or etch steps.
Sidewall spacers are typically formed by conformally depositing one or more layers of dielectric materials, such as an oxide (e.g., silicon dioxide) and/or a nitride (e.g., silicon nitride), to a desired thickness. However, the conformal deposition results in less material being deposited around the top corners of the gate structure, with rounding occurring. Then, an anisotropic etch process is performed to remove the dielectric material from the horizontal surfaces. While the etch process is selected to be anisotropic, the resulting sidewall spacers are inevitably tapered (i.e., not uniform) as a result of different deposition rates and etching rates near the upper and lower corners of the gate structure. Furthermore, as device sizes are scaled, devices (e.g., fins or gates) may become more vulnerable to defects as an indirect result of spacer etching.